Large digital electronic systems have many blocks of circuits that must communicate with each other. Communication is facilitated by the use of clocks that synchronize data transfers. Large systems may require many clock signals that are applied to large loads. These clocks are often synchronized to each other during clock generation. Higher operating speeds required that these clocks be accurate and precise.
Phase-locked loops (PLL's) are used to receive an external clock and to clean up any jitter or other signal distortions. In a PLL, an input clock is compared to a feedback clock that is generated by the PLL, and the feedback clock is altered by the PLL to match the input clock in phase and frequency.
One kind of clock generator that uses a PLL is known as a zero-delay buffer. Many clocks are generated from an input clock. A PLL is used to match a feedback clock to the input clock so that the feedback clock matches the phase and frequency of the input clock. The input clock's buffers are designed to match the buffering from the reference clock to the multiple output clocks that are generated. The PLL ensures that the phases of the output clocks match the input clock phase.
Although the delay through the PLL and buffers are non-zero, the delay is adjusted by the PLL to be exactly one clock period. Thus the delay appears to be zero, since the phases match and the delay is exactly one clock period. Skews in phases between the output clocks and the input clock are driven toward zero by the PLL in the zero-delay clock generator.
Single-ended clocks that could be carried on a single physical wire or trace were common when system speeds were lower. However, today's modern systems operate at blazingly fast speeds, and the single-ended clocks have too many signal distortions that can disrupt system operation. Interference from external sources such as electromagnetic interference can couple into the single-ended clock in noisy environments.
Differential clocks are carried on two physical wires or traces. The clock is represented by the difference in voltages on the two physical wires. Any external interference tends to couple in equally to both physical wires of a differential clock, so the interference tends to cancel out. Differential clocks can use relatively small voltage swings since differential receivers are quite sensitive. The smaller voltage swings reduce signal noise and distortion, producing more accurate clocks.
What is desired is a zero-delay clock generator for differential clocks. A zero-delay clock generator is desired that overcomes problems inherent in differential signals, such as common-mode drift.